/*
*	This is the PC regisiter
*	
*/

//TODO untested

module Reg_F(
	//Input Signal
	PCIn,
	EN,
	CLK,
	
	//Output Signal
	PCOut
);
	input EN,CLK;
	input[31:0] PCIn;
	
	output[31:0] PCOut;
	reg[31:0] PCOut;
	integer ClockCount;
	
	initial begin
		PCOut = 0;
		ClockCount = 0;
	end
	
	always @(posedge CLK) begin
		if(EN == 1 && ClockCount == 0) begin
			PCOut <= PCIn;
		end
		ClockCount = (ClockCount + 1)%2;
	end

endmodule
